The manufacture of semiconductor devices typically involves the deposition of layers of additive material (i.e., thin films) on a crystalline semiconductor substrate, such as single-crystal silicon or gallium arsenide. Adhesion of the layers of additive material to each other and to the semiconductor substrate is very important, because delamination of any one of the layers can lead to device failure. Therefore, the bonding strength of the various layers of additive material to each other and to the semiconductor substrate is critical, and testing is carried out as a part of manufacturing process development and quality control.
The general concepts of thin film adhesion measurements for multi-layered thin film structures have been described in several papers. See, for example, “Adhesion and Debonding of Multi-Layer Thin Film Structures”, R. H. Dauskardt et al., Engineering Fracture Mechanics, 61(1), pp. 141-162 (1998); “Quantitative Measurement of Interface Fracture Energy in Multi-Layer Thin Film Structures”, Q. Ma et al., Proceedings of MRS Annual Meeting, San Francisco, Calif., pp. 3-14 and 91-96 (1995); and “Adhesion and Reliability of Copper Interconnects with Ta and TaN Barrier Layers”, M. Lane et al., J. Mat. Res., 15(1), pp. 203-211 (2000).
With respect to thin films overlying relatively thick crystalline substrates, tile measurement of adhesion energy is primarily concerned with the macroscopic, or effective work of fracture per unit area required to separate an interface of interest. This may be quantified in terms of the critical strain energy release rate (debonding energy), Gc (typically in J/m2), which is a function of material properties, such as tile interfacial chemistry, adjacent microstructures, and elastic-plastic stress-strain behavior. Gc is also a function of mechanical properties, such as the loading mode mixity near to the debond tip (the ratio of shear to normal stresses). Other design parameters, including the surface morphology (roughness) and the thickness of adjacent thin film layers, may also have an important effect on adhesion.
The interface fracture resistance during debonding essentially depends upon two different energy absorbing processes. These are Go the near-tip work of fracture, and the energy dissipation which occurs in a zone surrounding the debond. In a region close to the debond crack tip, the intrinsic near-tip work of fracture Go provides a direct measure of the fracture process at the interface. Factors which contribute to Go include chemical bonding parameters from across the bond interface and/or micromechanical processes associated with the fracture mechanism.
Alternatively, in some instances, depending on the structure being tested, an energy dissipation zone appears due to factors such as the plasticity of adjacent ductile layers and the interaction of the debond faces behind the debond tip, Gzone. Interaction mechanism may involve frictional sliding of uneven contacting surfaces and even plastic stretching of unbroken ligaments across the fracture surfaces. Since these energy dissipation mechanisms typically act behind the debond crack tip, their effect increases with initial debond extension, until a steady-state interface fracture resistance is achieved. While such resistance curve behavior is often observed during interface failure, due to the scale of thin film structures, experimental detection of these effects is difficult and generally precluded. As a result, what is finally measured is:Gc=Go+Gzone (units: J/m2).
A significant limitation of many thin film adhesion measurement techniques, such as the peel test, blister test, indentation test, is that during debonding, residual stresses in the thin film relax and modify the measured adhesion energy. The effects of such relaxation on the measured adhesion values call be large, and although such effects can mathematically be included in an analysis, it is frequently difficult to accurately measure residual film stress of a very thin film present on a rigid substrate.
Thin film stress relaxation can be significantly reduced by preparing a sandwich structure where two pieces of the thin film on a rigid substrate are bonded together with the thin film being tested in the center of the sandwich. A small contribution to tile measured value of Gc will arise from elastic curvature of one of the rigid substrates supporting the thin film after debonding. However, the contribution of this effect to the debond driving energy has been shown to be minimal. Another advantage of the sandwiched sample configuration is the enablement of fracture mechanics-based tests to indicate the characteristics of subcritical debond-growth rate behavior which is associated with environmentally assisted or fatigue processes.
A commonly used adhesion test in the semiconductor industry is the four-point (bending) adhesion test. Apparatus for performing the four-point adhesion test is available, for example, from Dauskardt Technical Services (Menlo Park, Calif.). Referring to FIG. 1, which is a schematic top view of all assembly 130 used to perform the four-point adhesion test, a test specimen 100 is placed between dowel pins (114, 116, 118, 120) within bending fixture 111 members 110 and 112. The length of lest specimen 100 must be longer than the distance A between dowels 114 and 116, and typically ranges from about 30 mm to about 50 mm. Sandwich test specimen 100 consists of two semiconductor structures (102 and 104), each having a length of about 40 mm, a width of about 5 mm, and a thickness of about 0.8 mm. The two semiconductor structures have been sandwiched together, face-to-face, and bonded with a layer 106 of an epoxy adhesive in the middle of the sandwich. Typically, the epoxy adhesive layer thickness is about 5 μm to about 20 μm; however, depending on the clamping pressure placed on the sample during cure of the epoxy adhesive, the bonding layer may be as thin as about 2 μm. Bonding time and temperature and general sample preparation techniques are typically provided by the supplier of the epoxy adhesive. Higher bond temperatures and longer times within the specifications of tile manufacturer's recommended process generally produce stronger bonds.
After bonding of the sandwich test specimen 100, the exposed surfaces 103 and 105 of the sandwich test specimen 100 are typically a highly crystalline material, such as single crystal silicon or gallium arsenide. The upper surface 103 shown in FIG. 1 is then notched or grooved in a straight line across the entire width of the surface 103, from edge to edge. A notch (shown in FIG. 4D, for example) or a groove is typically cut into semiconductor structure 102 using a diamond saw. The notch or groove 108 is typically formed to have a maximum depth of about 500 μm into the surface 103 of semiconductor structure 102. Since the crystalline substrate material typically has a thickness of about 700 μm, about 200 μm of thickness of the crystalline substrate material remains overlying the thin film which is to be tested for adhesion to the crystalline substrate, for example.
The adhesion test is performed by applying a load to test fixture 111 at a constant displacement rate (about 0.01-0.5 μm/sec) to bend the test specimen 100, while carefully observing a load-displacement curve generated by the load cell which has a chassis and a piezo-electric actuator. A schematic illustration of a load-displacement curve is shown in FIG. 2, which is a graph 200 showing load (on tile vertical axis 202) versus displacement (on the horizontal axis 204). Region 208 of curve 206 shows slack being taken Lip in the loading system; region 210 shows linear elastic loading of the test specimen; region 212 shows the initiation of debonding at the notch formed in the test specimen; and region 214 shows debonding extending along the interface.
FIG. 3 is a graph 300 showing actual test data obtained during a four-point adhesion test of an Al/TiN/SiO2 interface structure. Region 308 of curve 306 shows a vertical pie-crack being formed; region 310 shows tile system behaving linear elastically with no debond extension; region 312 shows a crack kinking into the interface of interest; and region 314 shows the load plateauing at a constant displacement rate of 0.05 μm/sec.
The following equation is used to calculate the interface fracture energy:       G    c    =            21      ⁢              (                  1          -                      v            2                          )            ⁢              P        c        2            ⁢              L        2                    16      ⁢              Eb        2            ⁢              h        3            where v is Poisson's ratio for the crystalline substrate; L is the distance between the inner and outer dowel pins; E is the elastic modulus of tile substrate; b is the width of the beam; h is the half height of the beam (half of the height B of specimen 100 shown in FIG. 1), and Pc is the plateau load.
Test specimens for four-point adhesion testing (such as test specimen 100 shown in FIG. 1) are traditionally prepared according to the method depicted in FIGS. 4A through 4D. Referring to FIG. 4A, two sections, 402 and 404, of a semiconductor structure to be evaluated are bonded together face-to-face using an adhesive, to form the combined structure illustrated. Semiconductor structure sections 402 and 404 have equal dimensions (in this case, 40 mm×40 mm). The semiconductor structure typically consists of a crystalline substrate (such as single-crystal silicon or gallium arsenide) with at least one overlying layer of a additive material (not shown) in the form of a thin film (or films) of an additive material (or additive materials) which is (are) different from the substrate material. When semiconductor structure sections 402 and 404 are bonded, they are bonded with the more crystalline substrate side of each semiconductor-structure facing outward.
Following curing of the adhesive, the bonded structure 400 (shown in FIG. 4A) is diced, typically using a diamond saw, into test specimens 408 having the desired dimensions (in this case, 5 mm×40 mm), as shown in FIG. 4B. Following dicing, the side edge 410 of the test specimen 408 must be polished in order to eliminate defects from the side edge of the test specimen. If the side edge of the test specimen includes any stress-inducing defects, the test specimen will break almost immediately when load is applied during the performance of the four-point adhesion test, providing no meaningful adhesion data. To reduce the probability that stress-inducing defects are present on the side edges of the sawed test specimen, the side edges are polished, as illustrated in FIG. 4C. Polishing is typically performed using sand papers, going from coarse to fine, where a liquid may be used in contact with the specimen surface, to protect the surface being polished and to dissipate the heat generated during polishing. Typically, the liquid is water or alcohol. The surface roughness of the polished surface is controlled normally to be less than 5 μm.
After polishing of the side edges, a notch 412 is cut into the exposed surface of semiconductor structure 402, typically using a diamond saw, as illustrated in FIG. 4D. The notch 412 extends in a straight line across the entire width of test specimen 408, from one long edge 407 to the opposing long edge 409 of test specimen 408. The notch 412 is typically formed to have a depth of about 500 μm into the upper surface 403 of semiconductor structure 402. The function of the notch 412 is as a break point during bending of test specimen 408 during the performance of the four-point adhesion test described above.
In an alternative sample preparation method, each of the two semiconductor structure specimens are initially cut to the desired test specimen size, and then are bonded together in the same manner. The resulting test specimens are then polished and notched, as shown in FIGS. 4C and 4D.
The test specimen preparation methods described above provide consistent results in the four-point adhesion test (typical standard deviation for Gc is less than 0.5). However, these sample preparation methods are very time-consuming. Cutting of the notch to the desired depth and length is a tedious, difficult, and time-consuming step. In addition, polishing of the test specimen side edges prior to performance of the adhesion test is also very time consuming, making the specimens expensive to fabricate and delaying the time by which data may become available. Polishing of the test specimen side edges may also cause film contamination and/or changes in the film-substrate interface.
To make the sample preparation method less expensive, and to enable immediate testing for quality control purposes, a reliable, straightforward test specimen preparation method is needed. By reliable it is meant that the test specimens prepared by the new method should provide four-point adhesion test results which are at least as consistent as those obtained using samples prepared according to the traditional sample preparation methods described above.